Resistive memory, such as resistive random access memory (ReRAM or RRAM) generally includes a plurality of resistive memory cells. Such cells may be in the form of a two terminal device in which a comparatively insulating switching layer or medium is positioned between two conductive electrodes. In some instances, devices include one transistor (1T) or one diode (1D) along with one resistor (1R), resulting in 1T1R or 1D1R configurations. The resistive memory cells of RRAM can change between two different states, a high resistance state (HRS) which may be representative of an OFF or 0 state; and a low resistance state (LRS) which may be representative of an ON or a 1 state. In many instances a reset process is used to switch one or more cells of the RRAM device to the HRS using a reset voltage, and a set process is used to switch one or more cells of RRAM device to the LRS using a set voltage.
Some resistive memory devices operate based on the formation and breakage of filamentary channels (hereinafter, filaments) within the switching layer of individual resistive memory cells. Such devices, referred to herein as filamentary resistive memory, require the execution of an initial forming process, during which a relatively high voltage stress (known as a forming voltage) is applied to initially cause vacancies within the switching layer of a resistive memory cell to form one or more filaments. Such filaments may provide low resistance pathways between the conductive electrodes of the cell, and thus may place the cell in a low resistance state. After the forming process, the filaments may be broken and reformed via the application of reset and set voltages, respectively, so as to toggle the cell between a high resistance and a low resistance state.
While existing filamentary resistive memory has shown some promise, the execution of the forming process can result in the production of an unpredictable number and distribution of filaments within the switching layer of a resistive memory cell. For example, execution of the forming process may produce a first (e.g. 5) number filaments that are homogenously distributed within the switching layer of one resistive memory cell, but may produce a second (e.g., 8) filaments that are randomly or inhomogeneously distributed in another resistive memory cell. Moreover the size of the filaments created by the forming process may vary significantly within and/or among the plurality of resistive memory cells of a filamentary resistive memory device. As a result, the electrical characteristics (e.g., set and/or reset voltages) of the resistive memory cells of such devices may vary considerably from one another.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.